Pixel design and evaluation in CMOS image sensor technology

A chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor (APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses. Besides, structures to study the influence of crosstalk between pixels have been incorporated

Live demonstration: Real-time high dynamic range video acquisition using in-pixel adaptive content-aware tone mapping compression

This demonstration targets the acquisition of realtime video sequences involving High Dynamic Range (HDR) scenes. Adaptation to different illumination conditions while preserving contrast is achieved by using a sensor chip, which implements an adaptive content-aware tone mapping compression algorithm by using in-pixel circuitry. Its response gets adapted to changing illumination conditions by using at each frame a statistical estimation of the light distribution, which is derived from the HDR histogram calculated at the previous frame. This method allows adaptive HDR video, while capable to capture very large DR scenes including moving objects.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad IPT-2011-1625-430000Junta de Andalucía TIC 2338-201

CMOS 2.4μm chaotic oscillator: Experimental verification of chaotic encryption of audio

The Letter reports the first experimental verification of chaotic encryption of audio using custom monolithic chaotic oscillators. We use Gm-C techniques to realise a chaotic modulator/ demodulator IC that implements a 3rd-order nonlinear differential equation. This has been fabricated in 2.4μm double-poly technology and includes on-chip tuning circuitry based on amplitude detection. Measurements demonstrate how to exploit the synchronisation between two of these ICs for encrypted transmission

Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas

This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage via the data provided by a tactile sensor. Some implementations use different layers of piezoresistive and piezoelectric materials to build upon the raw sensor and obtain the static (pressure) as well as the dynamic (slippage) information. In this paper, a simple raw sensor is used, and a circuitry is implemented, which is able to extract the dynamic information from a single piezoresistive layer. The circuitry was inspired by structures found in human skin and retina, as they are biological systems made up of a dense network of receptors. It is largely based on an artificial retina , which is able to detect motion by using relatively simple spatial temporal dynamics. The circuitry was adapted to respond in the bandwidth of microvibrations produced by early slippage, resembling human skin. Experimental measurements from a chip implemented in a 0.35-mum four-metal two-poly standard CMOS process are presented to show both the performance of the building blocks included in each processing node and the operation of the whole system as a detector of early slippage.Ministerio de Economía y Competitividad TEC2006-12376-C02-01Gobierno de España TEC2006- 1572

Integrated circuit interface for artificial skins

Artificial sensitive skins are intended to emulate the human skin to improve the skills of robots and machinery in complex unstructured environments. They are basically smart arrays of pressure sensors. As in the case of artificial retinas, one problem to solve is the management of the huge amount of information that such arrays provide, especially if this information should be used by a central processing unit to implement some control algorithms. An approach to manage such information is to increment the signal processing performed close to the sensor in order to extract the useful information and reduce the errors caused by long wires. This paper proposes the use of voltage to frequency converters to implement a quite straightforward analog to digital conversion as front end interface to digital circuitry in a smart tactile sensor. The circuitry commonly implemented to read out the information from a piezoresistive tactile sensor can be modified to turn it into an array of voltage to frequency converters. This is carried out in this paper, where the feasibility of the idea is shown through simulations and its performance is discussed.Gobierno de España TEC2006-12376-C02-01, TEC2006-1572

Macromodelling for analog design and robustness boosting in bio-inspired computing models

Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads to a netlist of more than 100.000 nodes for a small array of 100×150 pixels. Moreover, introducing an optical input in the low level simulation is nowadays not feasible with standard electrical simulation environments. Given that, to accomplish the task of integrating those systems in silicon to build compact, low power consuming, and reliable systems, a previous step in the standard analog electronic design flux should be introduced. Here a methodology to make the translation from the biological model to circuit-level specifications for electronic design is proposed. The purpose is to include non ideal effects as mismatching, noise, leakages, supply degradation, feedthrough, and temperature of operation in a high level description of the implementation, in order to accomplish behavioural simulations that require less computational effort and resources. A particular case study is presented, the analog electronic implementation of the locust's Lobula Giant Movement Detector (LGMD), a neural structure that fires a collision alarm based on visual information. The final goal is a collision threat detection vision system on-chip for automotive applications.European Union IST-2001-38097, TIC2003 - 09817-C02-0

A mixed-signal early vision chip with embedded image and programming memories and digital I/O

From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (∼ 7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame

A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V

Robust high-accuracy high-speed continuous-time CMOS current comparator

The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5pA) and high-speed for low input currents (8ns at 50nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date

Bifurcations and synchronization using an integrated programmable chaotic circuit

This paper presents a CMOS chip which can act as an autonomous stand-alone unit to generate different real-time chaotic behaviors by changing a few external bias currents. In particular, by changing one of these bias currents, the chip provides different examples of a period-doubling route to chaos. We present experimental orbits and attractors, time waveforms and power spectra measured from the chip. By using two chip units, experiments on synchronization can be carried out as well in real-time. Measurements are presented for the following synchronization schemes: linear coupling, drive-response and inverse system. Experimental statistical characterizations associated to these schemes are also presented. We also outline the possible use of the chip for chaotic encryption of audio signals. Finally, for completeness, the paper includes also a brief description of the chip design procedure and its internal circuitry